This invention relates to mixed-signal converters of the sigma-delta noise shaping type, and more particularly, to mixed-signal analog-to-digital converter that employs a common-mode voltage feedback circuit.
Sigma-delta analog-to-digital converters (ADCs) provide for a means to achieve high resolution and low distortion at a relatively low cost compared to traditional Nyquist converters. The high resolution is achieved by oversampling the input signal and shaping the quantization noise in the band of interest into higher frequency region. The higher frequency noise can then be digitally filtered out by the subsequent digital filter stages. The resulting data is then down sampled to the desired sample rate at the output of the converter.
Typically, an audio sigma-delta ADC is implemented using discrete-time circuits such as switched capacitors for the following reasons. Switched capacitor circuits offer low sensitivity to clock jitter and are readily scalable with sampling rate. Moreover, tracking of coefficients of the loop is inherently good due to good matching of capacitors. However, due to the discrete-time nature, the converter suffers from harmonic distortion primarily caused by signal-dependent glitches captured by the sampling capacitors of the first integrator. In highly-integrated circuits such as a digital signal processor (DSP) with on-chip converters, it is very difficult to contain these undesirable glitches since the DSP is running at a much higher clock rate than the converter. Furthermore, for high performance converters, over 100 dB of signal-to-noise ratio (SNR), the sampling capacitors have to be large to reduce the thermal noise. Such a large sampling network emits current glitches back into the signal source which leads to electromagnetic interference (EMI).
Sigma-delta analog-to-digital converters are commonly designed using fully differential circuits to achieve good power supply rejection ratio, immunity to on-chip couplings, clock feed-through, charge injections, even-order harmonic distortions and other second-order non-ideal effects. Such fully differential circuits require a defined common-mode voltage to establish the proper operating point.
In a traditional fully-differential continuous-time sigma-delta converter with current-steering feedback DAC, the internal common-mode voltage of the integrator in the first stage of the converter is undefined when the input signal is AC coupled. When the input is DC coupled, the common voltage is defined by the external circuit. This voltage may not be the same as the desirable internal common-mode and may significantly degrade the performance of the converter.
Another problem with fully differential continuous-time ADC is the common-mode offset current from the feedback DAC. Since there is no mechanism for correcting this offset, both the positive and negative outputs of the differential integrator can peg to either positive or negative supply.
Yet another problem is that the input resistors of the integrator are built on chip, they may have mismatch as much as 1 percent. When a differential input signal, even from a balanced source, is applied to the ADC, the resistor mismatch will create a common-mode voltage swing at the summing junctions of the amplifier in the integrator. This voltage swing is a significant source of harmonic distortion in the converter.
FIG. 1 illustrates a simplified model of a 4-bit, 2nd-order sigma delta analog-to-digital converter with a continuous-time first-stage used in this invention. The setup primarily comprises a first summer circuit 101, continuous-time integrator 102, a second summer circuit 103, switched capacitor DAC 106, switched capacitor integrator 104, and current steering DAC 108. The continuous-time implementation of the first stage in the converter is much less susceptible to on-chip couplings than a switched capacitor implementation. Hence, the converter can be integrated into larger scale circuits in deep sub-micron processes without significant degradation in performance.
More over, since the input impedance is pure resistive, the circuit does not emit high frequency current glitches back to the external source. This yields a much lower electromagnetic interference (EMI) compared to a switched capacitor implementation. Hence, the converter is easier to use in EMI sensitive applications such as automotive systems.
FIGS. 2a–b illustrate two different approaches to implement the first stage of the converter. FIG. 2a shows the first approach which includes a fully-differential amplifier 202 with built-in output common-mode voltage control circuit, a pair of integrating capacitors 204 and 206, and a pair of input resistor 208 and 210. The current steering feedback DAC in FIG. 1 is also included as a part of the first stage.
FIG. 2b illustrates the second approach which comprises two single-ended amplifiers 212 and 214, a pair of capacitors 216 and 218, and a pair of resistors 220 and 222, and the feedback DAC. The positive input terminals of the amplifiers are connected to a reference voltage Vref 224.
FIG. 3 illustrates the implementation of a typical thermometer-code DAC used as the feedback DAC in the design. It consists of 2 PMOS devices MP1 302 and MP2 304, and 16 NMOS devices MN0 306 through MN15 308 (which form a bank of switching current cells, such as a 16 cell thermometer style DAC implementation). The PMOS devices 302 and 304 are biased by a voltage Vbias1 305, and the NMOS devices 306 and 308 are biased up by a voltage Vbias2 310. PMOS devices MP1 302 and MP2 304 are connected to the positive 312 and negative 314 DAC output terminals respectively. Each of these PMOS devices 302 and 304 conducts a current of magnitude I/2. Each of the NMOS devices MN0 306 to MN15 308 is connected to the positive 312 or negative 314 DAC output via a switch controlled by the data bit 316 or the complimentary data bit 318 respectively. Each NMOS device 306 or 308 conducts a current of magnitude 1/16.
In normal operation, when the DAC thermometer-code data input is at the logical value zero, eight bits are set to “1” and eight bits are set to “0”. Therefore, the net output current delivered by the DAC is theoretically zero. In practice, however, there is a net CM offset current at the DAC output 318. This is due to mismatch between the push and pull current sources.
There are at least two problems with the approach of FIG. 2a. First, while the output of the integrator has a common mode (CM) voltage defined by a feedback circuit, the input CM voltage depends on the input source. When a DC coupled source is connected to the input of the converter, the CM of the source will define the operating point at input of the converter. However, the DAC has a net CM offset current due to circuit imperfection, wherein this current creates a voltage across the resistors R1 208 and R2 210. In this case, the voltage at the summing junctions of the amplifier may be different than the intended value and may bring the amplifier out of the linear range. Moreover, the DAC is designed to give the optimal thermal noise performance since it is one of the dominant noise sources in the converter. This implies that saturation voltage of the NMOS devices is almost near the internal CM value. Any significant decrease of the CM voltage at the summing junctions of the amplifier will bring the DAC of out the saturation region and will significantly degrade the converter distortion measurements.
Second, due to process imperfections and layout mismatch, R1 208 may differ from R2 210 by an error as much as 1%. When a differential signal is applied to the ADC input, the summing junctions of the amplifier will see a CM swing. This CM swing will cause second-order harmonic distortion in the ADC output.
FIG. 2b illustrates an instrumentation style implementation. The approach in FIG. 2b does not suffer from the above-mentioned resistor mismatch problem associated with the circuit of FIG. 1, but it does require an output and an input CM feedback circuit. Moreover, it consumes more power and silicon area, and has 3 dB more noise than the first approach (of FIG. 1). Therefore, it is more advantageous to implement the first approach in the ADC design.
A technique to shift the common-mode voltage in a low-voltage system is presented in the paper to Duque-Carillo et al. entitled, “Input common-mode feedback technique for very low voltage CMOS amplifiers.” The circuit described by Duque-Carillo et al. has the ability to source and sink current and acts as a CM current attenuator so that the summing junctions can operate at a different CM voltage than that of the external signal source. However, implementation of such a circuit in a continuous-time integrator significantly degrades the signal-to-noise ratio (SNR) of the converter. This penalty comes directly as a result of the addition of the push-pull current sources in the mentioned technique. Since the noise gain of these devices is unity, the full noise strength of the CM attenuator circuit will appear at the output.
In the design of the ADC, the main noise sources are the feedback DAC and the input resistors. These components are optimized to yield the target SNR. If the mentioned technique is implemented, then the DAC has to be re-optimized to meet the target noise performance. This will lead to bigger chip area and higher power consumption. The impact becomes even more significant in smaller geometry processes such as 0.18u and below.
Whatever the precise merits, features, and advantages of the above cited references, none of them achieves or fulfills the purposes of the present invention. The present invention solves the above-mentioned problems via a small feedback circuit to stabilize the common-mode voltage of the first integrator and set it to a proper level.